In semiconductor memory, proper operation of the memory is based on the correct timing of various internal command, data, and clock signals. For example, in writing data to memory internal clock signals that clock data path circuitry to latch write data may need to be provided with specific timing relationships with internal write command signals to properly enable the data path circuitry to provide the latched write data for writing to memory. If the timing of the internal write command signal is not such that the data path circuitry is enabled at the time the internal clock signal clocks the data path circuitry to provide the write data at an expected time, the write command may be inadvertently ignored or the write data provided to the memory may not be correct (e.g., the write data is associated with another command).
Thus, internal clock, data, and write command paths should be designed to provide propagation delays for the respective signals to account for latency, for example, write latency between receipt of a write command and receipt of the write data for the write command. Other examples of commands that may require the correct timing of internal clock, data, and command signals for proper operation include, for example, read commands and on-die termination enable commands.
An example conventional approach to maintaining the timing of internal write command, data, and clock signals is modeling both the clock and data path, and the write command path to have the same propagation delay using, for instance, a plurality of logic gates, such as inverters or buffers. Because logic gates may add a relative small amount of delay, the number of gates used may often be higher than desirable.